1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of reducing reprogramming time, and a programming method thereof.
2. Discussion of Related Art
It is well known that nonvolatile semiconductor memory devices can permanently store data in memory cells when an external power goes off, and they are typically used in applications for mask read only memory (MROM), programmable read only memory (PROM), erasable and programmable read only memory (EPROM) and electrically erasable and programmable read only memory (EEPROM) in the nonvolatile memory device. In case of MROM, PROM or EPROM, users cannot easily erase or reprogram stored data because the erasing or reprogramming of the stored data is performed on the board of the memory device. However, in case of EEPROM, users can more easily perform the erase or reprogramming operation, because the EEPROM can be electrically erased and reprogrammed repeatedly, through the application of higher than normal electrical voltage. Therefore, the EEPROMs are used in numerous applications, such as system program storage devices or auxiliary memory devices requiring frequent data renewal. Recently, EEPROMs having a more compact size and capable of operating at high speed are needed in various fields, such as electronic devices controlled by computers or microprocessors, or in a battery powered computer system such as a portable or laptop computer.
To fulfill such need, a NOR-gate type flash EEPROM having a flash erase function has been proposed. The NOR-gate type flash EEPROMs can perform faster write and read operations than NAND type or AND type EEPROMs.
FIG. 9A shows a vertical cross-section of a memory cell transistor in a conventional NOR-gate type flash memory. An n-type source region 3 is formed apart from an n-type drain region 4 on a p-type substrate 2, a p-type channel region is formed between the source region 3 and the drain region 4. On the p-type channel region, a floating gate electrode 6 insulated with a thin insulating layer 7 of less than 100 angstroms and a control gate 8 insulated with another insulating layer 9 are formed in sequence.
FIG. 9B is a table showing voltages applied to various nodes of the memory cell transistor of FIG. 9A during program, erase, erase repair and read modes of operation.
At the program mode, hot electrons are injected from the channel region adjacent the drain region 4 to the floating gate electrode 6. At this time, as shown in FIG. 9B, a high voltage, for example, 10 V is applied to Vg of the control gate electrode 8 and a voltage for generating the hot electrons, for example, 5-6V is applied to Vd of the drain region 4, while the source region 3 and the p-type substrate region 2 are grounded. When negative charge is sufficiently accumulated at the floating gate electrode 6, the memory cell transistor has a higher threshold voltage. On the other hand, at the read mode, a positive voltage, for instance, 1V is applied to Vd of the drain region 4 and a predetermined voltage, for instance, 4.5V is applied to Vg of the control gate electrode 8, while the source region 3 and the substrate region 2 are grounded. During the read mode, the memory cell transistor having the higher threshold voltage remains in an off state, so called xe2x80x9coff-cellxe2x80x9d, therefore current flowing from the drain region 4 to the source region 3 is prevented. At this time, the threshold voltage is about 6-7V.
During erase mode, a Fowler-Nordheim tunneling phenomenon (hereinafter referred to as F-N tunneling) is generated from a bulk region formed at the substrate to the control gate electrode 8. For the F-N tunneling, a high negative voltage, for example, xe2x88x9210V is applied to Vg of the control gate electrode 8 and a voltage for generating the F-N tunneling, for example, 5V is applied to Vb of the bulk region as shown in FIG. 9B. At this time, the impedance of the drain region 4 is high for increasing the effect of the erase operation. Accordingly, a strong magnetic field is formed between the control gate electrode 8 and the bulk region, and the F-N tunneling is generated. Accordingly, the negative charge contained at the floating gate electrode 6 is discharged to the source region 3. It is known that the F-N tunneling happens when the magnetic field of 6-7 MV/cm is applied to the conductive layer between insulating layers. In the memory cell transistor of FIG. 9A, the insulating layer 7 has the thickness of 100 angstroms for generating the F-N tunneling. As a result of the erase operation, the memory cell transistor has a lower threshold voltage.
In a conventional flash memory, the bulk regions of a plurality of cells are commonly connected for high integration, so that the plurality of cells is simultaneously erased during the erase operation. An erase unit is determined according to an amount of dividing of the bulk region. For instance, an erase operation can be performed by 64K byte, and it is called a sector.
During read mode, the memory cell having the lower threshold voltage by the erase operation remains on because a current path is formed from a drain region to a source region. At this time, the memory cell transistor is called an xe2x80x9con-cellxe2x80x9d. The erased memory cell transistors have a threshold voltage of about 1V-3V. However, during the erase mode wherein the threshold voltage of the memory cell transistors is decreased, the threshold voltage can be less than 0V, instead of 1V-3V. This is due to the uniformity at the plurality of memory cell transistors. Those memory cell transistors having the threshold voltage of less than 0V are named xe2x80x9cover-erasedxe2x80x9d cells, which require curing operations (hereinafter erase-repair operations) for raising the threshold voltage to about 1V-3V. At the erase-repair mode, a positive voltage, for example, 2V-5V is applied to Vg of the control gate electrode 8 and a positive voltage, for example, 6V-9V is applied to Vd of the drain region 4, as shown in FIG. 9B, while the source region 3 and the substrate 2 are grounded in the over erased memory cell transistor. As a result, a smaller amount of negative charge, comparing to that of the program mode, is accumulated at the floating gate electrode 6, and the threshold voltage is about 1V-3V.
FIG. 10 is a graph showing the threshold voltage of memory cell transistors according to the program, erase and erase-repair modes. The horizontal axis indicates the threshold voltages of memory cell transistors, and the vertical axis indicates the distribution of the threshold voltage level. If programmed under the same conditions as in FIG. 9B, the off-cells can have a threshold voltage of approximately 5.2V to 7V while the on-cells can have a threshold voltage of approximately 1V to 3V.
Hereinafter, the operations of the conventional EEPROM will be described. When a program command is inputted from outside, a program checking operation is performed to determine whether the program operation has been completed. The program checking operation checks the current threshold voltage of memory cell transistors to be programmed. If any one of the memory cell transistors is not programmed, a program operation, that is, the hot electron injection is performed. On the other hand, if all the memory cell transistors are programmed, the program is completed and additional programming is not performed. The number of memory cell transistors to be programmed at one time is determined by the capacity of high voltage to be applied to the drain of each memory cell transistor. For instance, the total number of memory cell transistors to be programmed is divided by m (m is a natural number) to optimize the number of memory cell transistors to be programmed at one time. Accordingly, if the total number of the memory cell transistors is 16 and m is 8, the number of memory cell transistors to be programmed at one time will be 2. In general, if one word (16 bits) is to be programmed, and m is 8, and the number of cells to be programmed at one time is 2. It is referred to a 2-bit program hereinafter. After the programming is performed eight times by the unit of 2 bits, the program checking operation will be performed to check whether all the memory cells are completely programmed. If any one of the memory cells fails to be programmed, the reprogramming of the memory cell is performed. Meanwhile, if all the memory cells are completely programmed, or if the number of program loops reaches its maximum value, the programming of the memory cells is completed. In a second programming, that is, in the reprogramming, the 2-bit program operation will be performed 8 times again. At this time, high voltage is not applied to the drain region 4 of the previously programmed memory cell transistors, and the drain region 4 is in a program prohibiting state. When the second program operation is finished, the program checking operation is repeated.
As described above, in the conventional program operation, the time for the whole program increases in proportion to the number of programming to be repeated, because the same programming is performed at the second program operation regardless of the number of program prohibited cells. For instance, if a third programming is performed at the memory cell transistors, the total number of programming is twenty four times, i.e., 3 multiplied by 8. As a result, the programming time increases, and this limits a high-speed operation of the memory device. Therefore, there is a need to minimize the programming time.
It is an object of the present invention to solve the above problems and provide a method for reducing programming time of a NOR-type nonvolatile semiconductor device.
It is another object of the present invention to provide a nonvolatile semiconductor device capable of minimizing programming time.
It is still another object of the present invention to provide a semiconductor memory device and a related method for reducing reprogramming time.
In accordance with the first aspect of the present invention, there is provided a method for programming a plurality of memory cells of a nonvolatile semiconductor memory device in response to input data having a plurality of bit information comprising the steps of: programming the plurality of memory cells by units of n bits, wherein n is an integer not less than 2; checking whether programming of the plurality of memory cells is complete the programming operation; increasing the units by multiplying the n bits by 2 if any memory cell fails the programming operation; and reprogramming the plurality of memory cells by the units of the multiplied bits. In the method, if all the memory cells complete the programming operation or the number of programming gets to the maximum value, the programming of the plurality of memory cells are finished if all the memory cells complete the programming operation. The nonvolatile semiconductor memory device is preferably a NOR type flash EEPROM.
In accordance with another aspect of the present invention, there is provided a method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprising the steps of: programming the plurality of memory cells by raising threshold voltage of each memory cell, wherein the programming is performed by n-bit units, wherein n is an integer not less than 2; checking a threshold voltage of each programmed memory cell for determining whether the programmed memory cell complete the programming operation; increasing the number of bits in the units by multiplying the n by 2 if the threshold of any one memory cell among the programmed memory cells is below a predetermined level; reprogramming the plurality of memory cells by the units of the multiplied bits.
In accordance with further aspect of the present invention, there is provided a nonvolatile semiconductor memory device having a plurality of memory cells, in which each of the plurality of memory cells is programmed in response to input data having a plurality of bit information, the nonvolatile semiconductor device comprising: program means for performing program operations of the plurality of memory cells by n-bit units, wherein n is an integer not less than 2; checking means for checking the programmed memory cells to determine all the memory cells complete the programming operation; multiplying means for multiplying the n by 2 if any memory cell fails the programming operation; wherein the program means performs reprogramming of the plurality of memory cells by the units of the multiplied bits.